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Calm |
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(20:52 13/2/2001)
Gulli (23:43 13/2/2001)
jess (08:52 14/2/2001)
[Steve] (12:56 14/2/2001)
monkeyson (13:33 14/2/2001)
rich (13:58 15/6/2002)
guy (17:59 15/2/2001)
ams (19:51 15/2/2001)
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Hmm... |
Message #2077, posted at 20:52, 13/2/2001 |
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Must be a storm a comin.
Its awfully quiet here. |
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Gulli |
Message #2078, posted at 23:43, 13/2/2001, in reply to message #2077 |
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Must be a storm a comin.
Its awfully quiet here. I thought my ISP had messed up big this time! No new posts for two or three days. What happened? (or is about to happen). |
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jess |
Message #2079, posted at 08:52, 14/2/2001, in reply to message #2078 |
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Omega???? |
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[Steve] |
Message #2080, posted at 12:56, 14/2/2001, in reply to message #2079 |
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What's one of them then? |
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monkeyson |
Message #2081, posted at 13:33, 14/2/2001, in reply to message #2080 |
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I've not heard anything from MD yet. Has anyone got an order confirmation recently? I may have to ring up and badger them. |
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guy |
Message #2083, posted at 17:59, 15/2/2001, in reply to message #2082 |
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"... they were going down the LPFGA route rather than wait for their own design chipset to be quote]
produced ... March is the latest estimate for delivery." will this affect performance? (dusts Psion Series 5 off and pops in new batteries - at least it's 4 times the beast my A5000 is) |
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ams |
Message #2084, posted at 19:51, 15/2/2001, in reply to message #2083 |
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Full custom ASIC is usually the way to go. But optimised FPGA work can be very nearly as good. The first cut (test) version is usually slower and written in a hardware description language like VHDL, further iterations are then "floor planned" to optimise on chip routing to get best performance. I'd imagine MD already have a VHDL (or Verilog) description and will probably need to re-do some of the optimisations they did for their ASIC version. There is no reason why the release hardware should not be "close" to the performance of the ASIC version, although ASICs always have an edge (against that they take longer to develop, have a higher initial cost, but when purchased in quantity are less expensive than FPGA's). To even suggest a March delivery there should be an FPGA based prototype for people to look at soon. I'd still be a lot happer to see a prototype reviewed by someone independant - and soon so as to build confidence in a imminent release, and also it may give MD a chance to get some tweaking done and get some constructive feedback. Does anyone know what FPGA technology they are using (that'll be a good guide to the probable performance to expect) ? |
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rich |
Message #2082, posted at 13:58, 15/6/2002, in reply to message #2081 |
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On the Archive mailing list, from Adrian Warrick (via Jon Hall on the Acorn Arcade list  "I received a confirmation of my order shortly after it was placed.For your information, I telephoned at the end of last week and was told that they were going down the LPFGA route rather than wait for their own design chipset to be produced. Apparently, this will be at extra cost to THEM not us. March is the latest estimate for delivery." |
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